The use of spare components to replace defective components on semiconductor integrated circuit chips, generally referred to as "redundancy," has been increasingly utilized in recent years. The yield of good chips from a given wafer is strongly influenced by the size and number of defects that occur on the wafer. Such defects include defects in the silicon semiconductor crystal material that forms the substrate, as well as defects in oxide layers and conductors. Defects have become increasingly significant as the size of the individual components (that is the transistors, conductors, storage capacitors, resistors, and other components) becomes smaller relative to the size of the defects, and also as the overall area of the chip increases; both effects tending to increase the severity of the defect problem.
Fortunately, techniques have been developed to isolate defective portions of a circuit and substitute spare portions. Typical are the schemes described in U.S. Pat Nos. 3,753,235, 3,753,244 and 4,047,163 which require considerable additional circuitry. The techniques of the '235 and '244 patents provide a defective-word address store and a comparator circuit which disables a defective line of cells in an addressable array and directs signals for that store to an extra line of cells. The '244 stores the address of a defective cell by selectively open-circuiting wire links (fuses) of a read only memory connected to the comparator circuit using a bias current. The '235 stores the defective-cell address by grounding certain inputs of the comparator circuit. The '163 patent discloses a technique for substituting individual storage cells from a redundant array in place of a particular defective cell in the array. The technique of the '163 patent includes a storage means such as a programmed logic array which stores the row and column address location of each defective cell. This storage means sends an inhibit signal to inhibit normal cell selection and instead cause the selection of a redundant cell.
In U.S. Pat. No. 4,228,528 of Cenker et al. fusible links are melted using a laser beam to thereby disconnect a defective row or column of memory cells. This technique imposes minimum feature geometry requirements on the fusible links and further requires that the fusible links be physically spaced (isolated) from sensitive circuitry (e.g., the memory cells and logic) to avoid damage to surrounding circuitry by the laser beam. Practical application of such a technique would limit workers from reducing the surface dimensions of the fusible links along with the surrounding circuitry, in other words, would limit the "scalability" of such a redundant circuit technique. Moreover, multiple links must be cut to encode a spare row or column as a replacement for a particular row or column. Further, the laser vaporization requires extra processing steps including etching a window in a coating layer and subsequently closing the window.
However, the '528 patent recognizes certain considerations which are important for a defect-tolerant memory. In addition to the considerations identified in the '528 patent, an important consideration not heretofore adequately addressed in the art is whether the circuitry which enables the inclusion of a redundant array can be scaled along with the memory circuit and surrounding circuitry. Moreover, such circuitry should be implemented on the row or column pitch, that is, parallel to either the rows or columns of the cell array. Furthermore, the programming by which a redundant array is substituted for a defective array should be virtually program free and not impact on the speed of the memory. The present invention addresses these and other issues.